Unlocking RISC-V Security: A Novel Fault Injection Framework

Research teams from Politecnico di Torino and CEA-List have collaboratively published a technical paper, titled 'InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment.' This innovative framework is specifically designed to tackle the complexities of fault injection attacks, which pose a significant threat to hardware security by inducing malicious faults in computation or storage.

The InjectV framework offers a developer-oriented approach, leveraging architectural-level simulation to systematically assess vulnerability. Built on the gem5 simulator, it enables precise and guided fault injection at critical execution points, such as control-flow decisions, counters, and comparisons. With the capability to simulate diverse attack scenarios, including transient fault attacks in registers and memory, InjectV paves the way for enhanced security evaluation.

Experimental results, as demonstrated on security benchmarks from the FISSC suite, show InjectV's efficacy in identifying fault-injection points. Notably, it achieves a 95.8% time-saving advantage over traditional fault injection approaches, underscoring its potential in pre-silicon development.